Mam problem z symulacją działania układu w ModelSim, gdy używam IP softlvds.
Podczas generowania IP wychodzą 2 błędy(załącznik err1.png), ale koniec końców moduł działa poprawnie (przy testowaniu programu na sprzęcie).
Podczas próby przeprowadzenia symulacji w ModelSIM otrzymuję komunikat o 4 błędach:
Kod: Zaznacz cały
# do Thd_run_msim_rtl_vhdl.do
# if ![file isdirectory Thd_iputf_libs] {
# file mkdir Thd_iputf_libs
# }
#
# if {[file exists rtl_work]} {
# vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim ALTERA vmap 10.4b Lib Mapping Utility 2015.05 May 27 2015
# vmap -modelsim_quiet work rtl_work
# Copying C:/altera/15.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied C:/altera/15.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini.
# Updated modelsim.ini.
#
###### Libraries for IPUTF cores
###### End libraries for IPUTF cores
###### MIF file copy and HDL compilation commands for IPUTF cores
#
#
# vcom "C:/Users/deerj/OneDrive/Dokumenty/Altera/Thd_LVDS_test/lvds_sim/lvds.vhd"
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 19:09:00 on Apr 16,2016
# vcom -reportprogress 300 C:/Users/deerj/OneDrive/Dokumenty/Altera/Thd_LVDS_test/lvds_sim/lvds.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity lvds_ddio_out_1qd
# -- Compiling architecture RTL of lvds_ddio_out_1qd
# -- Compiling entity lvds_ddio_out_vpd
# -- Compiling architecture RTL of lvds_ddio_out_vpd
# -- Compiling entity lvds_cmpr_jqb
# -- Compiling architecture RTL of lvds_cmpr_jqb
# -- Compiling entity lvds_cmpr_qge
# -- Compiling architecture RTL of lvds_cmpr_qge
# -- Compiling entity lvds_cntr_cjd
# -- Compiling architecture RTL of lvds_cntr_cjd
# -- Compiling entity lvds_shift_reg_p7e
# -- Compiling architecture RTL of lvds_shift_reg_p7e
# -- Compiling entity lvds_shift_reg_d6e
# -- Compiling architecture RTL of lvds_shift_reg_d6e
# -- Loading package NUMERIC_STD
# -- Compiling entity lvds
# -- Compiling architecture RTL of lvds
# End time: 19:09:00 on Apr 16,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
#
# vcom -93 -work work {C:/Users/deerj/OneDrive/Dokumenty/Altera/Thd_LVDS_test/Thd.vhd}
# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015
# Start time: 19:09:00 on Apr 16,2016
# vcom -reportprogress 300 -93 -work work C:/Users/deerj/OneDrive/Dokumenty/Altera/Thd_LVDS_test/Thd.vhd
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity thd
# -- Compiling architecture bechavioral of thd
# End time: 19:09:00 on Apr 16,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
#
vsim work.thd
# vsim work.thd
# Start time: 19:09:45 on Apr 16,2016
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading work.thd(bechavioral)
# Loading ieee.numeric_std(body)
# Loading work.lvds(rtl)
# Loading work.lvds_ddio_out_1qd(rtl)
# Loading fiftyfivenm.fiftyfivenm_ddio_out(behavior)
# ** Error: (vsim-3033) nofile(38): Instantiation of 'dffeas' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /thd/U0/ddio_out/loop0(0)/ddio_outa/inst File: nofile
# Searched libraries:
# C:/altera/15.1/modelsim_ase/altera/vhdl/fiftyfivenm
# ** Error: (vsim-3033) nofile(38): Instantiation of 'dffeas' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /thd/U0/ddio_out/loop0(1)/ddio_outa/inst File: nofile
# Searched libraries:
# C:/altera/15.1/modelsim_ase/altera/vhdl/fiftyfivenm
# ** Error: (vsim-3033) nofile(38): Instantiation of 'dffeas' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /thd/U0/ddio_out/loop0(2)/ddio_outa/inst File: nofile
# Searched libraries:
# C:/altera/15.1/modelsim_ase/altera/vhdl/fiftyfivenm
# Loading work.lvds_ddio_out_vpd(rtl)
# ** Error: (vsim-3033) nofile(38): Instantiation of 'dffeas' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /thd/U0/outclock_ddio/ddio_outa/inst File: nofile
# Searched libraries:
# C:/altera/15.1/modelsim_ase/altera/vhdl/fiftyfivenm
# Loading work.lvds_cmpr_jqb(rtl)
# Loading work.lvds_cntr_cjd(rtl)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading fiftyfivenm.fiftyfivenm_atom_pack(body)
# Loading fiftyfivenm.fiftyfivenm_lcell_comb(vital_lcell_comb)
# Loading work.lvds_cmpr_qge(rtl)
# Loading work.lvds_shift_reg_p7e(rtl)
# Loading work.lvds_shift_reg_d6e(rtl)
# Loading fiftyfivenm.fiftyfivenm_pllpack(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading fiftyfivenm.fiftyfivenm_pll(vital_pll)
# Loading fiftyfivenm.fiftyfivenm_mn_cntr(behave)
# Loading fiftyfivenm.fiftyfivenm_scale_cntr(behave)
# Error loading design
# End time: 19:09:45 on Apr 16,2016, Elapsed time: 0:00:00
# Errors: 4, Warnings: 0
Bardzo proszę o pomoc