Obsługa jest prosta, do wejść A i B podłączamy enkoder.
Do wejścia CLK - zegar.
Mamy 2 wyjścia:
d_out - informuje nas o kierunku obrotu, jak jest 1 to kręcimy w jedną stronę, jak 0 to w drugą stronę.
c_out - na tym wyjściu pojawia się impuls informujący że enkoder wykonał jeden pełny krok.
Kod: Zaznacz cały
----------------------------------------------------------------------------------
-- Engineer: PROTON
-- Create Date: 20:23:32 01/09/2014
-- Module Name: encoder - Behavioral
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity encoder is
port(
A : in std_logic;
B : in std_logic;
CLK : in std_logic;
c_out : out std_logic;
d_out : out std_logic
);
end encoder;
architecture Behavioral of encoder is
constant S00 : std_logic_vector(3 downto 0) := "0000";
constant S01 : std_logic_vector(3 downto 0) := "0001";
constant S02 : std_logic_vector(3 downto 0) := "0010";
constant S03 : std_logic_vector(3 downto 0) := "0011";
constant S44 : std_logic_vector(3 downto 0) := "0100";
constant S10 : std_logic_vector(3 downto 0) := "0110";
constant S20 : std_logic_vector(3 downto 0) := "0111";
constant S30 : std_logic_vector(3 downto 0) := "1000";
begin
process(CLK)
variable stan : std_logic_vector(3 downto 0) := ( others => '0');
begin
if CLK ' event and CLK = '1' then
case stan is
when S00 =>
c_out <= '0';
d_out <= '0';
if A = '1' and B = '0' then
stan := S01;
elsif A = '0' and B = '1' then
stan := S10;
else
stan := S00;
end if;
when S01 =>
if A = '1' and B = '1' then
stan := S02;
elsif A = '1' and B = '0' then
stan := S01;
else
stan := S00;
end if;
when S02 =>
if A = '0' and B = '1' then
stan := S03;
elsif A = '1' and B = '1' then
stan := S02;
else
stan := S00;
end if;
when S03 =>
if A= '0' and B = '0' then
stan := S44;
d_out <= '1';
elsif A = '0' and B = '1' then
stan := S03;
else
stan := S00;
end if;
when S44 =>
c_out <= '1';
stan := S00;
when S10 =>
if A = '1' and B = '1' then
stan := S20;
elsif A = '0' and B = '1' then
stan := S10;
else
stan := S00;
end if;
when S20 =>
if A = '1' and B = '0' then
stan := S30;
elsif A = '1' and B = '1' then
stan := S20;
else
stan := S00;
end if;
when S30 =>
if A= '0' and B = '0' then
stan := S44;
--d_out <= '0';
elsif A = '1' and B = '0' then
stan := S30;
else
stan := S00;
end if;
when others =>
stan := S00;
end case;
end if;
end process;
end Behavioral;